SV Rule Checker

UVM File (apb_slv_agent_tb.sv)

`timescale 1ns/1ps

/* verilator lint_off IMPORTSTAR */
import uvm_pkg::*;
`include "uvm_macros.svh"
/* verilator lint_on IMPORTSTAR */

//////////////////////////////////////////////////////////////
// INTERFACE
//////////////////////////////////////////////////////////////

interface apb_intf(input bit clk, input bit rst);

  logic [20:0] sysbus;
  logic [7:0]  prdata;

  // DRIVER clocking block
  clocking driver_cb @(posedge clk);
    output sysbus;
    input  prdata;
  endclocking

  // MONITOR clocking block
  clocking monitor_cb @(posedge clk);
    input sysbus;
    input prdata;
  endclocking

  modport DRIVER  (clocking driver_cb, input clk);
  modport MONITOR (clocking monitor_cb, input clk);

endinterface

//////////////////////////////////////////////////////////////
// SEQUENCE ITEM
//////////////////////////////////////////////////////////////

class apb_seq_item extends uvm_sequence_item;

  rand bit [20:0] sysbus;
       bit [7:0]  prdata;

  `uvm_object_utils_begin(apb_seq_item)
    `uvm_field_int(sysbus, UVM_ALL_ON)
    `uvm_field_int(prdata, UVM_ALL_ON)
  `uvm_object_utils_end

  function new(string name="apb_seq_item");
    super.new(name);
  endfunction

endclass

//////////////////////////////////////////////////////////////
// SEQUENCER
//////////////////////////////////////////////////////////////

class apb_sequencer extends uvm_sequencer #(apb_seq_item);
  `uvm_component_utils(apb_sequencer)

  function new(string name="apb_sequencer", uvm_component parent);
    super.new(name, parent);
  endfunction
endclass

//////////////////////////////////////////////////////////////
// DRIVER
//////////////////////////////////////////////////////////////

`define DRIV_IF intf.driver_cb

class apb_driver extends uvm_driver #(apb_seq_item);

  `uvm_component_utils(apb_driver)

  virtual apb_intf intf;

  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db#(virtual apb_intf)::get(this,"","intf",intf))
      `uvm_fatal("NO_VIF","Virtual interface not set")
  endfunction

  task run_phase(uvm_phase phase);
    forever begin
      seq_item_port.get_next_item(req);
      drive();
      seq_item_port.item_done();
    end
  endtask

  task drive();
    @(posedge intf.clk);
    `DRIV_IF.sysbus <= req.sysbus;
    @(posedge intf.clk);
    req.prdata = `DRIV_IF.prdata;
  endtask

endclass

//////////////////////////////////////////////////////////////
// MONITOR
//////////////////////////////////////////////////////////////

class apb_monitor extends uvm_monitor;

  `uvm_component_utils(apb_monitor)

  virtual apb_intf intf;
  uvm_analysis_port #(apb_seq_item) item_collected_port;
  apb_seq_item trans_collected;

  function new(string name, uvm_component parent);
    super.new(name,parent);
    item_collected_port = new("item_collected_port",this);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db#(virtual apb_intf)::get(this,"","intf",intf))
      `uvm_fatal("NO_VIF","Virtual interface not set")
  endfunction

  task run_phase(uvm_phase phase);
    forever begin
      trans_collected = apb_seq_item::type_id::create("trans_collected");
      @(posedge intf.clk);
      trans_collected.sysbus = intf.monitor_cb.sysbus;
      @(posedge intf.clk);
      trans_collected.prdata = intf.monitor_cb.prdata;
      item_collected_port.write(trans_collected);
    end
  endtask

endclass

//////////////////////////////////////////////////////////////
// AGENT
//////////////////////////////////////////////////////////////

class apb_agent extends uvm_agent;

  `uvm_component_utils(apb_agent)

  apb_sequencer sequencer;
  apb_driver    driver;
  apb_monitor   monitor;

  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    monitor = apb_monitor::type_id::create("monitor", this);

    if(get_is_active() == UVM_ACTIVE) begin
      driver    = apb_driver::type_id::create("driver", this);
      sequencer = apb_sequencer::type_id::create("sequencer", this);
    end
  endfunction

  function void connect_phase(uvm_phase phase);
    if(get_is_active() == UVM_ACTIVE)
      driver.seq_item_port.connect(sequencer.seq_item_export);
  endfunction

endclass

//////////////////////////////////////////////////////////////
// SCOREBOARD
//////////////////////////////////////////////////////////////

class apb_scoreboard extends uvm_scoreboard;

  `uvm_component_utils(apb_scoreboard)

  uvm_analysis_imp #(apb_seq_item, apb_scoreboard) item_collected_export;

  function new(string name, uvm_component parent);
    super.new(name,parent);
    item_collected_export = new("item_collected_export",this);
  endfunction

  function void write(apb_seq_item t);
    `uvm_info("SCOREBOARD", $sformatf("Received sysbus=%0h prdata=%0h", t.sysbus, t.prdata), UVM_LOW)
  endfunction

endclass

//////////////////////////////////////////////////////////////
// ENVIRONMENT
//////////////////////////////////////////////////////////////

class apb_env extends uvm_env;

  `uvm_component_utils(apb_env)

  apb_agent      agent;
  apb_scoreboard scb;

  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agent = apb_agent::type_id::create("agent", this);
    scb   = apb_scoreboard::type_id::create("scb", this);
  endfunction

  function void connect_phase(uvm_phase phase);
    agent.monitor.item_collected_port.connect(scb.item_collected_export);
  endfunction

endclass

//////////////////////////////////////////////////////////////
// SEQUENCE
//////////////////////////////////////////////////////////////

class apb_sequence extends uvm_sequence #(apb_seq_item);

  `uvm_object_utils(apb_sequence)

  function new(string name="apb_sequence");
    super.new(name);
  endfunction

  task body();
    repeat(2) begin
      req = apb_seq_item::type_id::create("req");
      start_item(req);
      req.randomize();
      finish_item(req);
    end
  endtask

endclass

//////////////////////////////////////////////////////////////
// TEST
//////////////////////////////////////////////////////////////

class apb_test extends uvm_test;

  `uvm_component_utils(apb_test)

  apb_env env;

  function new(string name="apb_test",uvm_component parent=null);
    super.new(name,parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env = apb_env::type_id::create("env", this);
  endfunction

endclass

//////////////////////////////////////////////////////////////
// SIMPLE DUT
//////////////////////////////////////////////////////////////

module top_apb(
  input clk,
  input rst,
  input [20:0] sysbus,
  output reg [7:0] prdata
);
  always @(posedge clk)
    prdata <= sysbus[7:0];
endmodule

//////////////////////////////////////////////////////////////
// TOP
//////////////////////////////////////////////////////////////

module apb_testbench_top;

  bit clk;
  bit rst;

  always #5 clk = ~clk;

  initial begin
    rst = 1;
    #10 rst = 0;
  end

  apb_intf intf(clk,rst);

  top_apb DUT (
    .clk(intf.clk),
    .rst(rst),
    .sysbus(intf.sysbus),
    .prdata(intf.prdata)
  );

  initial begin
    uvm_config_db#(virtual apb_intf)::set(null,"*","intf",intf);
    run_test("apb_test");
  end

endmodule

DUT File (apb_mst_sys_dut.sv)

module bridge_apb ( output reg  psel,// select signals
                    output reg  penable,      // enable signal
                    output reg  pwrite, // write signal
                    output reg [7:0] paddr,  // 8-bit address
                    output reg [7:0] pwdata, // 8-bit data                    	
                    input clk,   // clock signal
                    input rst, // negedge reset
		    input [20:0] system_bus,       
	            input [7:0] prdata    
                    );
  
  parameter IDLE = 2'd0, SETUP = 2'd1, ACCESS  = 2'd2;
  parameter READ= 2'd0, WRITE=2'd1;
  
  reg [1:0] state; 
  reg [7:0] pwdata1;
  reg [7:0] paddr1;
  reg penable1;
  reg b_psel;

  reg [7:0] sys_data;
  reg [7:0] sys_addr;
  reg [1:0] sys_kind;
 // reg  [ 1 : 0 ]      sel slave;
  reg sys_active;     
 
  
  always @ ( * )
  begin
    sys_data = system_bus [7:0];
    sys_addr = system_bus [15:8];
  //  sel slave   = system_bus [ 17 : 16 ];
    sys_kind = system_bus [19:18];
    sys_active =system_bus [20];  
  end

  always @ (posedge clk or negedge rst)
  begin//read or write
    
    if(!rst)
     pwrite <= 1'b0;
    
    else 
    begin
      if ( state == SETUP )
       begin
	 case (sys_kind)
	    READ :
	     begin
	       pwrite  <= 1'b0;
	     end
	    WRITE :
	     begin
 	       pwrite  <= 1'b1;
	     end
	  endcase
     end  
end   // always @ (posedge pclk)
 end  //reset condition
  
  
  always @ ( posedge clk or negedge rst )
  begin 
    if(!rst)
      state <= IDLE;
    else
    
  // FSM state transition

  begin 
    paddr1   = 0;
   // pwdata1  = 0;
    penable1 = 0;
    b_psel    = 0;
    state = IDLE; 

    case ( state )
      
      IDLE :  
        begin// : idle_state
          if (sys_active == 1)
          begin
              state = SETUP;
              b_psel = 4'b0;
              penable1 = 0;
          end
          else 
	      penable1 = 0;
	   end
      
      SETUP :
        begin 
           penable1  = 0;
	   paddr1 = sys_addr;
    	   pwdata1 = sys_data;
           state  = ACCESS;
        
        if ( ( sys_kind == 2'b01 ) || ( sys_kind == 2'b10 ) ) 
	             b_psel = 1'b1;
	      else if ( ( sys_kind == 2'b00 ) || ( sys_kind == 2'b11 ) )
	             state  = IDLE ;
	     end
      


      ACCESS  :
        begin            
                penable1 = 1;  
	        b_psel = 1; 
	        
	        // write
          if( sys_kind == 2'b01)
          begin             
            paddr1    = sys_addr;
            pwdata1   = sys_data;
          end 
          
          //read
          else if ( sys_kind == 2'b10 )         
                paddr1   = sys_addr;
        
          // state transition to SETUP in case of back to back write etc.,
           
          if ( ( sys_kind == 2'b01 ) || ( sys_kind == 2'b10 ) )
  	           state = SETUP;
	        else    
              state  = IDLE;          
        end //: active_state  
      
      default : state = IDLE; 
    endcase // case ( pre_state )
    
  end //: state_change
end
//assigning the internal signal values to the outputs of SLAVE

  always @ (posedge clk or negedge rst)
  begin
    if (!rst)
    begin
      psel <= 4'b0000;
      paddr <= 8'b0;
      pwdata <= 8'b0;
      penable   <= 1'b0;
      //sys_rd_data <= 8'b0;	
    end
    else if ((state == ACCESS )|| (state == SETUP) || ( sys_active == 0) )
    begin
      paddr   <= paddr1;
      pwdata  <= pwdata1;
      psel    <= b_psel;
      penable <= penable1;
      
    end
  end
  

endmodule

module slave_apb (  output reg [3:0] prdata, //dataout from slave 
                    input penable,// to enable read or write
                    input pwrite, // control signal 
                    input psel,  // select signal
                    input clk,   // posedge clk
                    input rst, // negedge reset              
                    input [7:0] paddr,  // 8-bit address            
                    input [7:0] pwdata  // 8-bit write data
                    );
  
parameter IDLE=2'b00,SETUP=2'b01,ACCESS=2'b10;


  reg [1:0]state;

  reg [7:0] slave [0:255];  // slaveory-256 bytes
  reg [7:0] prdata1;
  
  always @ (posedge clk or negedge rst )
  begin// : fsm_slave
    if (!rst)
      state = IDLE;
    else 
     begin
     prdata1 = 8'b0;
     case(state)
    
   
      IDLE   :
        begin //: idle_state
	  if ( ! penable )
	   begin
            if ( psel == 0 ) 
	     begin
              state = IDLE;
	      prdata1 = 8'b0;
             end
	    
            else if ( ( psel == 1 ) && ( penable == 0 ) )
             begin
              state = SETUP;
	     end 
	        
        end 
      end

      SETUP  :
        begin //: setup_state
	  
          if( ( psel == 1 ) && ( penable == 1) )
            begin
            state = ACCESS;
            end
        end 
      
      ACCESS :
        begin //: enable_state
	 
          if ( ( psel == 1 ) && ( penable == 0 ) )
            state  = SETUP;
	
          else
          begin //: no_transfer
            state  = IDLE;
          end //: no_transfer
          
	  if(!pwrite)        
            prdata1 = slave[paddr];
	  
          if (( psel == 0 ) && ( penable == 0 ))  
            state = IDLE;
	
        end //: enable_state
      
      default : state = IDLE;
    endcase
end

  end //: state_change
  
  always @ (posedge clk or negedge rst)
  begin 
    if (!rst)
    begin
      prdata = 8'b0;
    end  
    else
      if ( (state == ACCESS ) && ( pwrite == 0 ) )
        prdata = prdata1;
  end

  always @ (posedge clk or negedge rst)
  begin
    if ( (state == ACCESS) && (pwrite ==1) )
     begin
        slave [paddr] = pwdata; 
     end 
  end
  
endmodule

Output

Welcome to SV Rule Checker! (UVM Mode)

1. Default UVM and DUT files are loaded.
2. Click 'Run' to execute the simulation using UVM (Verilator).
3. You can also open your own files using the buttons in the header.